1. Field of the Invention
The present invention generally relates to a staticized flop circuit, and more particulary, to a dynamic-to-static converter of a staticized flop circuit which reduces glitching in a static output thereof.
2. Description of the Related Art
A conventional staticized flop circuit, an example of which is shown in FIGS. 1 and 2, functions to periodically evaluate a dynamic logic signal to produce a corresponding static output signal. This is necessary in the case where a dynamic circuit output is to interface with a static circuit, and thus the dynamic signal output must be staticized for application to the static circuit. FIG. 1 is a functional block diagram of such a circuit, whereas FIG. 2 is an exemplary component level circuit diagram of the same.
A logic circuit 102 receives at least one input A, B, . . . X to perform a logic operation on the same. The logic circuit 102 may be any logic circuit, such a MUX for example, that produces a dynamic output. In the example of FIG. 2, the logic circuit is implemented by transistors ML1 and ML2 which produce the logical NAND of inputs A and B at a dynamic node EVAL.
Together with the logic circuit 102, a precharger D 104, a latch D 106 and a ground switch 108 form a dynamic circuit. The precharger D 104 serves to precharge the dynamic node EVAL during each low pulse of a clock signal CLK, and may be implemented by a voltage source Vdd and a transistor MPRE as shown in FIG. 2. Conversely, the ground switch 108, which may be implemented by a transistor MGS, functions to conditionally discharge the dynamic node EVAL during each high pulse of the clock signal CLK. The discharge is conditional since the transistors ML1 and ML2 of the logic circuit 102 must be closed as well. The latch 106 may be composed of forward invertor INVD1 and feedback invertor INVD2, and functions to hold the voltage of the dynamic node EVAL for the case of EVAL-to-high.
The dynamic to static conversion takes place in the convertor 110. As shown in FIG. 2, the convertor may be formed of pull-down transistor MC1, an activation transistor MC2, and a pull-up transistor MC3. MC1 and MC3 basically form an inverter which is activated and deactivated by MC2. That is, if MC2 is on (activated) and EVAL is high, then MC3 is off and MC1 is on, thus pulling down the voltage at node Y to low. In contrast, if EVAL is low while MC2 is on, then MC3 is on and MC1 is off, thus pulling up the voltage at node Y to high. Also, when MC2 is off (deactivated), EVAL is precharge to high, and thus MC3 is off and the path to MC1 is cut off by MC2, and no change in the node Y potential takes place.
At the output of the dynamic-to-static convertor is a latch 112 and an output buffer 114. The latch 112 functions to latch the potential at static node Y and may include a forward invertor INVS1 and a feedback invertor INVS2. The output buffer 114 may be implemented by an output inverting buffer INVB.
In the circuits of FIGS. 1 and 2, the static node Y undergoes a transition responsive to an input transition. On the other hand, even in the absence of an input transition, the dynamic mode EVAL is precharged and is conditionally discharged every CLK cycle. This is described in greater detail below. In the discussion herein, logic "0" is low and is ground Vss, whereas logic "1" is high and is supply voltage Vdd.
First, a "precharge phase" is described which takes place when the clock CLK is low. Since CLK is low, MPRE is turned on and dynamic node EVAL is charged to high. This in turn puts MC3 in an off state and MC1 in an on state. However, since CLK is low, MC2 is off, and therefore both the pull-up path and the pull-down path of the converter 110 are shut off. The static node Y thus maintains its value, the voltage of which is held by the latch 112. When the CLK goes low at the precharge phase, the pulldown path of the converter is immediately shut-off. This action then isolates static node Y from any transition at dynamic node EVAL, and thus staticizes the circuit output.
The "evaluation phase", which occurs when the CLK goes high, will now be described. It is assumed for explanation purposes that the static node Y is initialized to high.
In a first case, either one or both of ML1 and ML2 is off, and thus EVAL remains high. That is, MGS turns on, but the pull-down path for node EVAL is cutoff by logic circuit 102. Also, the high dynamic node EVAL keeps MC1 on (and MC3 off), while the CLK turns on MC2. The pull-down path of node Y is thereby established, discharging node Y to low and switching the output to high.
In a second case, both ML1 and ML2 are on, and CLK turns on MGS to activate the pull-down path for node EVAL, thus causing EVAL to go low. At the same time, the CLK turns on MC2 which activates the pull down path for node Y. Thus, node EVAL and node Y are discharged almost simultaneously. When the dynamic node EVAL hits a threshold voltage, MC3 overpowers MC1, and the static node is charged back up to high, causing the output to go low.
It takes time for the dynamic node EVAL to discharge to the point where MC1 is shut off to block the pull-down action of node Y. This causes the node Y to glitch to low prior to being restored to high. This glitch is at least partially caused by the fact that the clock-to-q delay for the flop is not balanced for the two edges as shown below: EQU clk(r).fwdarw.out(r)=y(f)+out(r)=2 gate delay EQU clk(r).fwdarw.out(f)=eval(f)+y(r)+out(f)=3.5 gate delay
where clk(r).fwdarw.out(r) is the delay from the rise of CLK to the rise of the output; y(f) is a 1-gate delay occurring during a falling of node Y to low; out(r) is a 1-gate delay occurring during a rise of the output to high; clk(r).fwdarw.out(f) is the delay from the rise of CLK to the fall of the output; eval(f) is a 1.5 gate delay occurring during a falling of node EVAL to low; y(r) is a 1-gate delay occurring during a rising of node Y to high; and out(f) is a 1-gate delay occurring during a falling of the output to low.
In the equations above, eval(f) is a 1.5 gate delay. In fact, however, eval(f) can range from 1 to 2 gate delays depending on the number of nmos devices (embedded logic) contained in the evaluation stack of the logic circuit 102. A 2-device stack would equate to 1 gate delay, a 3-device stack would equate to a 1.5 gate delay, and a 4-device stack would equate to a 2 gate delay.
Glitching results at node Y when the previous value at node Y is high and the EVAL node evaluates to low. In this case, a zero-gate delay occurs in the activation of switch MC2 (driving by the clock), whereas a 1.5-gate or more delay occurs in the pull-down of node EVAL. This increases the pull-down time of node Y prior to its being pulled back up by action of the pull-up transistor MC3.
Glitching presents problems in several respects. For example, glitching raises power consumption and requires special care when conducting electromigration studies. Moreover, glitching reduces the noise margin for the circuit receiving the flop output.
In addition, the problems of glitch propagation are intensified for low-voltage applications. FIG. 3(a) illustrates the case where Vdd=1.8v, and FIG. 3(b) illustrates the case where Vdd=1.0v. It is a common practice to attempt to counter glitching by skewing the inverter of the output buffer by selecting a stronger (lower beta ratio) pull-down device MN. When Vdd=1.8v as in FIG. 3(a), the voltage drive for MN is Vgs-Vt=0.9v-0.5v=0.4v in the case of a 50% glitch in the node Y potential. By using a larger MN in the inverter, some reduction in the glitch magnitude is possible. On the other hand, at the lower supply voltage Vdd=1.0v as in FIG. 3(b), the voltage drive for MN is Vgs-Vt=0.5v-0.5v=0.0v (again in the case of a 50% glitch in the node Y potential). Thus, regardless of the size of MN, the pull-down device is cutoff and can no longer hold the node down, and the glitch therefore propagates much more easily.
There have been previous attempts to overcome or reduce the effects of glitching. One approach has been to speed up the discharge rate of the EVAL node by selecting large pull-down devices with low fanout for the EVAL node. This approach, while only minimally successful, increases the device area and power usage. Other designs include selecting a high beta ratio (i.e., a stronger pull-up) for MC3 relative to that of MC1 and MC2. Still other designs employ a high fanout on node Y by increasing the size of the output buffer INVB, or (as suggested above) a weakened pull-up (i.e. a small beta ratio) of the output buffer INVB to prevent propagation of the glitch. Nevertheless, any reduction in glitch magnitude is minimal with these approaches.